Reduced-complexity decoding implementation of QC-LDPC codes with modified shuffling

Abstract Layered decoding (LD) facilitates a partially parallel architecture for performing belief propagation (BP) algorithm low-density parity-check (LDPC) codes. Such schedule LDPC codes has, in general, reduced implementation complexity compared to fully and higher convergence rate both serial architectures, regardless of the codeword length or code-rate. In this paper, we introduce modified shuffling method which shuffles rows matrix (PCM) quasi-cyclic (QC-LDPC) code, yielding PCM each layer can be produced by circulation its above one symbol right. The proposed scheme additionally guarantees columns shuffled either zero weight single weight. This condition has key role further decreasing LD complexity. We show that due these two properties, number occupied look-up tables (LUTs) on field programmable gate array (FPGA) reduces about 93% consumed on-chip power nearly 80%, while bit error (BER) performance is maintained. only drawback degradation throughput, negligible low values $$E_b/N_0$$ Eb/N0 until BER 1e−6.